A data processing system that controls a large amount of memory will generally utilize a memory management system of some form. One commonly used memory management system provides memory circuits that translate the logical address output of a data processor to a physical address for the data processing system. The memory circuits utilized to perform this function include but are not limited to a Content Addressable Memory (CAM) circuit connected to a Random Access Memory (RAM) circuit along with a Control-Mechanism for controlling the loading of logical and physical addresses into the CAM and RAM arrays, respectively. The translation of a Logical Address, contained within the CAM, to a Physical Address, contained within the RAM, is speed critical since the speed of the data processing system is limited by the rate at which the data processor can access memory. FIG. 1 illustrates a prior art memory system 10 having a DC-Load 12, and a CAM array 14 connected to a RAM array 16 by Match-Lines. The CAM array 14 has of a plurality of CAM entries and RAM array 16 has a plurality of RAM entries with each CAM entry corresponding to a predetermined RAM entry.
Each CAM entry has a predetermined number of CAM cells, a Validity-bit cell, and an Input-Logic cell (not shown). A logical address input to CAM array 14 contains a predetermined number of individual logical address lines. The individual logical address lines are each connected to a predetermined CAM cell (not shown) of each CAM entry in CAM array 14. For example, a logical address line zero is connected to a CAM cell zero of each CAM entry in CAM array 14. Each CAM cell has a memory storage portion (not shown) and a compare logic portion (not shown). The memory storage portion has a storage cell that can be written. A Validity-bit cell (V) has a storage cell that can be written.
The compare logic portion contained within each CAM cell in CAM array 14 compares an individual logical address input of the CAM cell to the data stored within the storage portion of the CAM cell. If the individual logical address input matches the data stored within the storage portion of the CAM cell, the CAM cell compare logic allows the associated Match-Line to remain active. If the address input to the CAM cell does not matches the data stored within the storage portion of the CAM cell, the CAM cell compare logic deactivates the associated Match-Line.
The Match-Line for a CAM entry remains active in response to the connected DC-load under the following conditions. The first condition is that the Validity-bit cell of the CAM entry be active, meaning that the data stored within the storage portion of the CAM cell is valid and available for translation. The second condition for the Match-Line to remain active is that the logic state of the storage portion of the CAM cell match the logic state of the Logical Address input. When the above conditions are not met, the Match-Line is deactivated. When the Match-Line is deactivated, the DC-load connected to the Match-Line is consuming power.
Each RAM entry of RAM array 16 has a predetermined number of RAM cells. A physical address input to RAM array 16 contains a predetermined number of individual physical address lines. The individual physical address lines are each connected to one RAM cell for each RAM entry in RAM array 16. For example, physical address line zero is connected to RAM cell zero of each RAM entry of the RAM array 16.
For a translation operation, the Logical Address input to CAM array 14 is compared with each CAM entry in the CAM array and one of two conditions exists. There will either be a matching CAM entry (HIT) or no matching CAM entry (MISS). A HIT condition occurs when the Logical Address input matches a CAM entry with an active Valid-bit, and a MISS condition occurs when the Logical Address input does not match a CAM entry with an active Valid-bit.
When a HIT condition occurs, the Match-Line of the CAM entry that matched the Logical Address input remains active and thereby selects a predetermined RAM entry. The selected RAM entry then connects the contents of each RAM cell of the selected RAM entry to the Physical Address lines connected to RAM 16. The compare logic portion of each CAM cell of the CAM entries that did not match a Logical Address input will deactivate the associated Match-Line of the CAM entry thereby preventing the selection of a RAM entry from RAM array 16.
A write operation sequence begins with a Write-Select signal being activated. The Logical Address input to CAM array 14 is then stored in the storage portion of a selected CAM entry concurrently with the Validity-bit of the selected CAM entry being activated. The Match-Line of the selected CAM entry then becomes active in response to the connected DC-load, and the RAM entry connected to the active Match-Line is selected. The Physical Address at the input to RAM array 16 is then latched into the RAM cells of the selected RAM entry.
When a MISS condition occurs, a control mechanism associated with memory system 10 (not shown) will execute an algorithm using hardware and software that systematically searches external memory to locate a predetermined RAM entry. When the predetermined RAM entry is located in external memory, the control mechanism will write the CAM and RAM entries into the CAM array 14 and RAM array 16, respectively.
The power consumption associated with the DC-loads of each CAM entry is significant since all but one DC-load is consuming power during a translation and a write operation. Furthermore, since a common method of improving the translation speed of a CAM circuit is to increase the strength of the DC-load associated with each Match-Line of each CAM entry in CAM array 14, large CAM arrays that require large DC-loads to obtain the necessary speed become impractical because of the increased power requirements.
Memory system 10' of FIG. 2 is similar to memory system 10 of FIG. 1 and for the ease of illustration and discussion, functional blocks with the same number and the same signal names are used. There are two significant differences between the illustrated memory systems of FIG. 1 and FIG. 2. The first difference is the replacement of DC-load 12 with a Dynamic-load transistor 18 in FIG. 2. The Dynamic-load transistor 18 is illustrated as a transistor switch with a first current electrode connected to a power supply voltage V.sub.DD, a second current electrode connected to the Match-Line, and a control electrode connected to a timing control signal labeled ".phi.". The second difference between memory system 10 of FIG. 1 and memory system 10' of FIG. 2 is the addition of a plurality of OR gates, one per each CAM and RAM entry. One of the OR gates to an OR gate 20 illustrated in FIG. 2 and positioned between the CAM array 14 and the RAM array 16 OR gate 20 has a first input for receiving the Match-Line signal, a second input for receiving the Write-Select signal, and an output for providing a signal labeled "Word-Line" which is connected to a predetermined RAM entry.
For an address translation operation, the Write-Select signal from a control mechanism (not shown) is inactive and Dynamic-load transistor 18 activates the Match-Line during a predetermined time period when .phi. is active. Also when .phi. is active, the Logical Address input to the CAM array 14 is applied. When control signal .phi. is not active, the Logical Address input is compared with each CAM entry in CAM array 14. If there is a HIT, the Match-Line of the matching CAM entry will remain active thereby providing an active input to OR gate 20, which subsequently generates an active Word-Line signal. The active Word-Line signal thereby selects a predetermined RAM entry in RAM array 16 and the contents of each RAM cell of the selected RAM entry is connected to the Physical Address lines of RAM array 16. The compare logic portion of each CAM cell of the CAM entries that did not match the Logical Address input to CAM array 14 will then deactivate the associated Match-Line. Since the DC-load 12 of FIG. 1 was replaced by the Dynamic-load transistor 18 of FIG. 2, the power consumption problem associated with a DC-load to activate the Match-Line is eliminated.
For an address write operation, the Write-Select signal remains active during the write operation sequence. The active Write-Select signal enables the selected CAM entry to store the logical address input into the storage portion of the CAM cells of the selected CAM entry. The active Write-Select signal also activates the Word-Line signal which selects a predetermined RAM entry in RAM array 16. The Physical Address input to RAM array 16 is subsequently stored in the RAM cells of the selected RAM entry. At approximately the same time the Logical Address input to CAM array 14 is loaded into the storage portion of each CAM cell of the selected CAM entry, the Validity-bit of the selected CAM entry is activated. The power consumption during the write operation is essentially the same as for the address translation operation because the DC-load is replaced by the Dynamic-load. A significant difference between the memory system 10' of FIG. 2 and the memory system 10 of FIG. 1 is that the memory system 10' of FIG. 2 consumes less power when operating because of the use of a Dynamic-load transistor instead of a DC-load to activate the Match-Line for each of the CAM entries. Another difference between systems 10 and 10' is that the function of the Match-line is disabled in system 10' during an address write operation, thereby saving power.
Another similar memory system is taught by Uchiyma et al. in U.S. Pat. No. 4,646,271 entitled "Content Addressable Memory Having Dual Access Modes." Uchiyma et al. teach a memory system having a selector circuit coupled between a CAM array and a RAM array for concurrently addressing both the CAM and RAM arrays.